ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration

As industry moves towards many-core chips, networks-on-chip(NoCs) are emerging as the scalable fabric for interconnectingthe cores. With power now the first-order design constraint, earlystageestimation of NoC power has become crucially important.ORION [29] was amongst the first NoC power models released,and has since been fairly widely used for early-stage power estimationof NoCs. However, when validated against recent NoCprototypes – the Intel 80-core Teraflops chip and the Intel ScalableCommunications Core (SCC) chip – we saw significant deviationthat can lead to erroneous NoC design choices. Thisprompted our development of ORION 2.0, an extensive enhancementof the original ORION models which includes completelynew subcomponent power models, area models, as well as improvedand updated technology models. Validation against thetwo Intel chips confirms a substantial improvement in accuracyover the original ORION. A case study with these power modelsplugged within the COSI-OCC NoC design space explorationtool [23] confirms the need for, and value of, accurate early-stageNoC power estimation. To ensure the longevity of ORION 2.0,we will be releasing it wrapped within a semi-automated flow thatautomatically updates its models as new technology files becomeavailable.