Simulation of semiconductor wafer dicing induced faults on chips and their application as augmentation method for a deep learning based visual inspection system

In semiconductor wafer dicing, one particular area of interest is the process of visual inspection to detect manufacturing defects that occur throughout the manufacturing process. Emerging defect patterns are typically in the micrometer range, translating to barely visible defects in pixel size on high-resolution imagery. The availability of rarely occurring defects is generally limited due to the labor-intensive nature of the related, highly specialized annotation task. Therefore, this contribution proposes a hybrid system for wafer and chip image data synthesis utilizing wafer and dicing path templates for the synthetic generation of large quantities of labeled flawless and, rarely, faulty chip and dicing street imagery. These are utilized for subsequent deep learning based defect detection and classification by employing a residual neural network as the core classifier for our visual inspection system. Our results show promising prospects when the original image data are supplemented with synthesized images by creating so-called composite data sets. Compared to the system’s baseline on the original data set, an F1-score-based relative improvement of up to 3.98 times was achieved. Furthermore, a novel synthetic-composite leave-one-out cross-validation (SC-LOOCV) method is proposed as a means to analyze the quality of our synthesized data for each specific wafer type. Based on these experiments, we scored a relative improvement of up to 5.99. For all our wafer types, overall relative improvement factors of 1.99 (composite) and 2.83 (SC-LOOCV) highlight the benefits of our realized system.