A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits
| Year of publication: |
1994
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|---|---|
| Authors: | Andreatta, A.A. ; Ribeiro, C.C. |
| Published in: |
Annals of operations research. - New York, NY [u.a.] : Springer Science + Business Media, ISSN 0254-5330, ZDB-ID 2526293. - Vol. 50.1994, p. 1-36
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