A study of high-speed analog-computer performance (the astrac I system performance)

Increased interest in high-speed hybrid analog/digital computation has led to the development of the Arizona Statistical Repetitive Analog Computer (ASTRAC I), which employs inexpensive digital logic to control a high-speed repetitive analog computer. The design of the machine has been described elsewhere; this paper reports the results of the error analysis performed on the linear analog computing elements and digital timing circuits. The results are of particular interest for the design of new computing systems of this type.