ESTIMATING SPURIOUS POWER WHILE MAPPING K-LUT-BASED FPGA CIRCUITS

In this paper is presented a new approach for decreasing the spurious power consumption in K-LUT based FPGA implemented circuits. The approach is based on selective collapsing nodes in a direct acyclic graph (DAG) representing combinational or synchronous sequential circuits. It was used the simulation-based approach that estimates, using Monte Carlo experiment, the spurious switching activity of each net in the circuit. Traversing circuits in topological order, step by step best K-feasible cone are computed at the output of each node. Preserving the best depth of the circuits the mapping stage is done searching to minimize spurious switching power.