High-Level Synthesis Hardware Accelerators of Integer-pixel Motion Estimation of HEVC on SoC-FPGA Platform

Motion estimation entails the major computation complexity load and processing time in HEVC video encoder. Integer-pixel Motion Estimation (IME) consume more than 45% of the processing time. Therefore, this paper presents a High-Level Synthesis Hardware Accelerator for Integerpixel Motion Estimation of HEVC on Xilinx SoC-FPGA Platform. The hardware accelerator is three time faster than the corresponding software implementation with only 100 MHz clock frequency on Xilinx Zynq ZC702 FPGA.