Simulaneous order-lot pegging and wafer release planning for semiconductor wafer fabrication facilities
Seung-Kil Kim, Jae-Gon Kim and Hwa-Joong Kim
| Year of publication: |
2014
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|---|---|
| Authors: | Kim, Seung-kil ; Kim, Jae-gon ; Kim, Hwa-joong |
| Published in: |
International journal of production research. - London : Taylor & Francis, ISSN 0020-7543, ZDB-ID 160477-6. - Vol. 52.2014, 12 (15.6.), p. 3710-3724
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| Subject: | order-lot pegging | input release planning | semiconductor wafer fabrication | Lagrangian relaxation | total tardiness | sensitivity analysis | Halbleiterindustrie | Semiconductor industry | Halbleiter | Semiconductor | Scheduling-Verfahren | Scheduling problem | Produktionsplanung | Production planning | Mathematische Optimierung | Mathematical programming |
| Type of publication: | Article |
|---|---|
| Type of publication (narrower categories): | Aufsatz in Zeitschrift ; Article in journal |
| Language: | English |
| Source: | ECONIS - Online Catalogue of the ZBW |
Persistent link: https://www.econbiz.de/10010356948