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Search: subject:"Very large scale integration"
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VLSI
5
Entwurf
2
Very large scale integration
2
1979-1988
1
Dead space
1
Diskrete Mathematik
1
Electronics
1
Electronics industry
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Elektronik
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Elektronikindustrie
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Expertensystem
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Floorplanning
1
Halbleiter
1
Japan
1
Kombinatorische Optimierung
1
Layout <Mikroelektronik>
1
Nebenbedingung
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Quadratische Optimierung
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Reihenfolgeproblem
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Semiconductor
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Simulated annealing algorithm
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Standortproblem
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Technologiepolitik
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Very high speed integrated circuit
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Zuordnungsproblem
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Anand, S.
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Algorithms and combinatorics : study and research texts
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Comparative politics
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Computational Optimization and Applications
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Interner Bericht / Universität Kaiserslautern, Fachbereich Informatik
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USB Cologne (EcoSocSci)
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ECONIS (ZBW)
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Customized simulated annealing based decision algorithms for combinatorial optimization in VLSI floorplanning problem
Anand, S.
;
Saravanasankar, S.
;
Subbaraj, P.
- In:
Computational Optimization and Applications
52
(
2012
)
3
,
pp. 667-689
Modern
very
large
scale
integration
technology is based on fixed-outline floorplan constraints, mostly with an …
Persistent link: https://www.econbiz.de/10010847439
Saved in:
2
Location, scheduling, design and integer programming
Padberg, Manfred W.
;
Rijal, Minendra P.
-
1996
Persistent link: https://www.econbiz.de/10004306690
Saved in:
3
Paths, flows, and VLSI layout
Korte, Bernhard
(
contributor
)
-
1990
Persistent link: https://www.econbiz.de/10004103532
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4
State strength, industry structure, and industrial policy : American and Japanese experiences in microelectronics
Fong, Glenn Randall
- In:
Comparative politics
22
(
1990
)
3
,
pp. 273-299
Persistent link: https://www.econbiz.de/10001086223
Saved in:
5
EDIF notation for layout, circuit relations
Blödel, Joachim
(
contributor
)
-
1988
Persistent link: https://www.econbiz.de/10004062563
Saved in:
6
An artificial intelligence approach to VLSI routing
Joobbani, Rostam
-
1986
Persistent link: https://www.econbiz.de/10004561678
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