Design method for two-Stage CMOS operational amplifier applying load/miller capacitor compensation

CMOS operational amplifiers (Op-amp) are present integral components in various analog circuit systems. Adding frequency compensation elements is the only critical solution for avoiding Op-amp instability. This article presents a designed two-stage CMOS Op-amp using a miller capacitor, a nulling resistor, and a common-gate current buffer for compensation purposes. All the design parameters of the proposed Op-amp were determined based on the corresponding equations of gain, slew rate, phase margin, power dissipation, etc. In order to verify the parameter values, the developed Op-amp circuit was simulated in HSPICE, possessing two critical characteristics: Op-amp with miller capacitor and a robust bias circuit. Afterwards, the expected values from the theoretical section were compared with simulation results thus proving that the advanced method in this paper was validly designed and implemented. This technique promises a real-world scale Op-amp with high unity-gain, excessive input common-mode range voltage, reasonable gain bandwidth, and a practicable slew rate.