Hardware Implementation of 8b/10b Encoding System with On-Chip Verification in FPGA

This paper presents a fast and efficient implementation of the 8b/10b encoding and decoding algorithm, widely used in any networking for high speed serial data transfer. The hardware implementation of this 8b/10b encoding and decoding algorithm has been done in a Vertex 5 XCVLX5110T target device with the use of VHDL as the hardware description language. In order to confirm the expected behavior of the 8b/10b encoder and decoder circuitry, the implemented design was extensively simulated and synthesized for different FPGA devices both in Spartan and Virtex series from Xilinx viz., Spartan 3, Spartan 3AN, Virtex 5, etc. The novelty and contribution of this work are threefold: (i) Extensive simulation and synthesis of the design targeted for various Field-Programmable Gate Array (FPGA) devices, (ii) Complete hardware implementation of the encoder and decoder targeted to Virtex 5 board using device XCVLX5110T, (iii) Generation of Integrated Controller (ICON) core and Virtual Input/Output (VIO) core for the design and on-chip verification and analyzing using Chipscope Pro