Bayesian Decision Analysis for Optimizing Defect Inspection Strategy for Smart Semiconductor Manufacturing

In-line defect inspection is employed to monitor tool health via sampling an in-line processing lot every fixed period, and avoid suffering large quality loss when the production tools are abnormal. However, defect inspection is a time-consuming process including lot movement, defect scan, and review for trouble shooting that will prolong cycle time. Thus, optimizing defect inspection sampling plan including defect inspection lot reduction is critical to enhance fab productivity and maintain competitive advantages for semiconductor manufacturing companies. Little research has been done for the present problem. To fill the gaps, this study aims to develop a framework for optimizing defect scan sampling by integrating two solutions, in which this study firstly constructs an evaluation model for select the lot for defect inspection to enhance the information gain and then optimizes the sampling period allocation subject to the calculated risks for productivity and cycle time reduction. An empirical case study was conducted in a leading semiconductor manufacturing company for validation. The results have shown practical viability for implementation and thus significantly reducing the lots for defect inspection while maintaining yield and productivity